Shift registers are core circuit units of integrated circuits that are used in products such as thin film transistor liquid crystal displays (TFT-LCDs). A shift register provides sequential pulse signals to scanning lines of a TFT-LCD, so as to control on and off states of TFTs connected to the scanning lines.
Referring to FIG. 5, one such shift register unit 100 includes a first clock inversion circuit 110, an inverter 120, and a second clock inversion circuit 130. All transistors in the first clock inversion circuit 110, the inverter 120, and the second clock inversion circuit 130 are PMOS (P-channel metal oxide semiconductor) transistors. The first clock inversion circuit 110 receives an output signal VS from a pre-stage shift register unit (not shown). The output signal VS functions as a start signal.
The first clock inversion circuit 110 includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a first output V1, and a second output V2. The inverter 120 includes a fifth transistor P5 and a sixth transistor P6. The inverter 120 outputs an output signal that serves as a shift register signal V. The second clock inversion circuit 130 and the first clock inversion circuit 120 have similar structures. The second clock inversion circuit 130 includes a seventh transistor P7, an eighth transistor P8, a ninth transistor P9, and a tenth transistor P10.
Referring to FIG. 6, a sequence waveform diagram of pulse signals of the shift register unit 100 is shown. During a period t1, the inverter 120 and the second clock inversion circuit 130 perform a latch operation. During the latch operation, the sixth transistor P6 is switched off such that the shift register signal V of the inverter 120 keeps an original state of the previous stage. During a period t2, no latch operation is performed. The start signal VS is applied to the inverter 120, and the second clock inversion circuit 130 keeps the same state as the start signal VS. Furthermore, the first transistor P1 is switched on because the start signal VS jumps to a low voltage, such that the fifth transistor P5 is switched off and the sixth transistor P6 is switched on. Thus, the inverter 120 outputs the shift register signal V having a low level through the activated sixth transistor P6. During a period t3, the inverter 120 and the second clock inversion circuit 130 perform latch operation. The inverter 120 maintains output of a low level shift register signal V through the activated sixth transistor P6. During a period t4, no latch operation is performed. The inverter 120 stops output of the low-level shift register signal V.
The shift register unit 100 outputs a low level shift register signal during period t2, and at the same time, the next-stage shift register unit (not shown) also outputs a low level shift register signal. However, the shift register unit 100 installs so many transistors and other elements therein, which makes the layout thereof unduly complicated.
What is needed, therefore, is a shift register which can overcome the above-described deficiencies. What is also needed is an LCD device including the shift register.